Generally, an image sensor, which converts an optical image into an electrical signal, is classified as a charge coupled device (CCD) or a complementary metal oxide semiconductor (CMOS) image sensor.
The CCD includes a plurality of photo diodes PD for converting a light signal into an electrical signal arranged in a matrix form; a plurality of vertical charge coupled devices (VCCD) formed between the photodiodes and arranged in a vertical direction for vertically transferring charges generated at the respective photodiodes; a plurality of horizontal charge coupled devices (HCCD) for horizontally transferring the charges transferred from their respective VCCDs; and a sense amplifier for outputting the electrical signal by sensing the horizontally transferred charges.
The CCD, however, has several disadvantages such as complicated driving system, high power consumption, and a complicated fabrication process due to the plurality of photolithographic processes.
In addition, the CCD is also disadvantageous in miniaturizing the product because it is very difficult to integrate a control circuit, a signal processing circuit, an analog to digital (A/D) converter, etc, within a CCD chip.
To overcome the above disadvantages of the CCD, the CMOS image sensor has been highlighted as the next-generation image sensor.
The CMOS image sensor employs a switching mode that sequentially detects outputs of unit pixels using MOS transistors formed using CMOS technology. The switching mode is accomplished by forming MOS transistors corresponding to the number of the unit pixels on a semiconductor substrate and using a control circuit and a signal processing circuit as peripheral circuits.
That is, the CMOS image sensor displays an image by sequentially detecting electrical signals of the respective unit pixels through the switching mode, wherein each unit pixel is configured with a photodiode and MOS transistors.
Since the CMOS image sensor is fabricated using the CMOS technology, the CMOS image sensor has advantageous merits such as low power consumption, and a simple fabrication process in virtue of the relatively small number of photolithographic processes.
Further, because the CMOS image sensor enables a control circuit, a signal processing circuit, and an A/D converter to be integrated in the CMOS image sensor chip, it is advantageous in that a small sized product can be fabricated with ease.
Therefore, the CMOS image sensor is widely used for various applications such as a digital still camera and a digital video camera.
The CMOS image sensor is classified as a 3T type, a 4T type, or a 5T type, etc., according to the number of the transistors in each unit pixel. For example, the 3T type CMOS image sensor is configured with one photodiode and three transistors, and the 4T type CMOS image sensor is configured with one photodiode and four transistors.
A layout for a unit cell of the 4T type CMOS image sensor is described below with reference to FIGS. 1 and 2.
FIG. 1 is an equivalent circuit diagram of a related art 4T type CMOS image sensor, and FIG. 2 is a layout illustrating a unit cell of the 4T type CMOS image sensor.
Referring to FIG. 1, the unit pixel 100 of the CMOS image sensor includes a photodiode 10 acting as a photoelectric converter, and four transistors.
Herein, the four transistors are configured as a transfer transistor 20, a reset transistor 30, a drive transistor 40, and a select transistor 50. A load transistor 60 is electrically connected to an output terminal OUT of each of the unit pixels 100.
Reference symbols FD, Tx, Rx, and Sx denote a floating diffusion region, the gate voltage of the transfer transistor 20, the gate voltage of the reset transistor 30, and the gate voltage of the select transistor 50, respectively.
In the unit pixel of the related art 4T type CMOS image sensor illustrated in FIG. 2, an active region is defined by a solid line and a device isolation region is defined as the region not being the active region. The photodiode PD is formed at the wide portion of the active region, and gate electrodes 23, 33, 43 and 53 of the four transistors are formed overlapping the narrow portion of the active region.
That is, the transfer transistor 20, the reset transistor 30, the drive transistor 40 and the select transistor 50 are formed by the gate electrodes 23, 33, 43 and 53, respectively.
Herein, impurity ions are implanted onto the active area by each transistor 20, 30, 40 and 50 except directly below each gate electrode 23, 33, 43 and 53 to form source/drain regions (S/D) of each transistor.
FIGS. 3A to 3E are sectional views taken along line I-I′ illustrating a method for fabricating the related art CMOS image sensor.
Referring to FIG. 3A, an epitaxial process is performed to form a lightly doped p-type epitaxial layer 62 on a heavily doped p-type semiconductor substrate 61.
Subsequently, an active region and a device isolation region are defined in the semiconductor substrate 61, and a device isolation layer 63 is then formed on the device isolation region using a shallow trench isolation (STI) process.
An insulating layer and a conductive layer, e.g., a heavily doped polysilicon layer, are sequentially deposited on the entire surface of the epitaxial layer 62. Thereafter, the conductive layer and the insulating layer are selectively removed to form a gate electrode 65 and a gate insulating layer 64.
Referring to FIG. 3B, a first photoresist layer is coated on the entire surface of the semiconductor substrate 61, and is then patterned so as to expose blue, green, and red photodiode regions through exposure and development processes.
Afterwards, lightly doped n-type impurity ions are implanted onto the epitaxial layer 62 using the patterned first photoresist layer as a mask to form a lightly doped n-type diffusion region 67 for the blue, green, red photodiode regions.
Next, after the first photoresist layer is completely removed, an insulating layer is deposited on the entire surface of the semiconductor substrate 61 and an etch-back process is then performed to form spacers 68 on side surfaces of the gate electrode 65.
Thereafter, a second photoresist layer is coated on the entire surface of the semiconductor substrate 61, and is then patterned so as to cover the photodiode region but expose the source/drain regions of each transistor through exposure and development processes.
Subsequently, n-type impurity ions are implanted at high concentration onto the exposed source/drain regions using the patterned second photoresist layer as a mask to form an n-type diffusion region (floating diffusion region) 70.
Referring to FIG. 3C, the patterned second photoresist layer is removed. A third photoresist layer is coated on the entire surface of the semiconductor substrate 61, and thereafter it is patterned so as to expose the respective photodiode regions through exposure and development processes. Then, p-type impurity ions are implanted onto the photodiode region having the n-type diffusion region 67 using the patterned third photoresist layer as a mask so that a p-type diffusion region 72 is formed beneath the surface of the semiconductor substrate 61. Next, after the patterned third photoresist layer 71 is removed, a thermal treatment is performed on the semiconductor substrate 61 to diffuse the respective impurity diffusion regions.
However, the related art method for fabricating the CMOS image sensor has several problems as discussed below.
The etching process, which is performed for selectively removing the gate insulating layer and the conductive layer so as to form the gate electrode, causes damage to the semiconductor substrate at the region where the photodiode PD is formed.
Moreover, when the ion implantation process, e.g., the ion implantation for forming the source/drain regions, is formed on the damaged semiconductor substrate, the semiconductor substrate becomes more damaged due to the ion implantation process, which results in increasing a dark current of the unit pixel with respect to the photodiode formed in the damaged semiconductor substrate. Accordingly, the low light performance of the CMOS image sensor becomes degraded.